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| a Preliminary Technical Data FEATURES * Monotonic DNL < 1 LSB * Improved Accuracy at Zero Scale * Fast 2s Settling Time * Power ON Reset * 3-Wire Serial Data Input * 25MHz Data Load Rate * Internal Reference Voltage * +4.5V to +5.5V Single Supply Operation APPLICATIONS * Digital Control of Gain & Offset Two's Complement Dual, 12-Bit DACs AD5329 data bits clocked into the register will be transferred to the internal DAC register when the strobe input is returned to logic high. The output transfer equation is: VOUT = [(D-2048) / 4096 * VDACREF] + VBZ Where D is the 12-bit decimal data, and VOUT, VDACREF, VBZ are with respect to ground. The AD5329 is available in the compact 1.1mm thin SOIC-10 package. All parts are guaranteed to operate over the industrial temperature range of 0C to +70C. PIN CONFIGURATION V DD 1 SDA 2 NC 3 V OUTB 4 V OUTA 5 10 GND 9 SCLK 8 FSYNC 7 NC 6 V BZ GENERAL DESCRIPTION The AD5329 is a serial-input, dual 12-bit digital-to-analog converter that accepts two's complement digital coding. An internal voltage reference generates a stable 2V DACREF. The buffered DACREF output generates the system bipolar ground reference at pin VBZ. The bipolar DAC output swing programs over a 4VPP range. The device is specified for operation from +5 volts 10%. Data is loaded MSB first on the positive clock edge (SCLK) when the frame synch (FSYNC) input is active low. The serial clock input word is 16-bits with the MSB position containing an address bit. The last 12 Model AD5329KRM-REEL7 ORDERING GUIDE RES Temp Package Package (bits) Range Description Option 12 0/+70C SOIC-10 RM-10 FUNCTIONAL BLOCK DIAGRAM VBZ (VREF) VDD X2 VBZ + 2V VOUTA AD5329 +2V + VDACREF X2 VBZ - 2V VBZ + 2V VOUTB VBZ - 2V GND DECODER SW DRIVER A 12 DECODER SW DRIVER B 12 FSYNC EN ADDR DECODE SCLK A0 DAC A REGISTER DAC B REGISTER 12 SDI 16-Bit SERIAL INPUT REGISTER D11 ...............D0 Power On Reset REV PrC, 20 DEC 99 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax:617/326-8703 (c)Analog Devices, Inc., 1998 AD5329 -- SPECIFICATIONS ELECTRICAL CHARACTERISTICS (VDD = +5V10%, 0C < TA < +70C unless otherwise noted.) Parameter DC CHARACTERISTICS Resolution Differential Nonlinearity Error Integral Nonlinearity Error Integral Nonlinearity Error Full-Scale Temperature Coefficient2 Positive-Full-Scale Error Bipolar-Zero-Scale Error Negative-Full-Scale Error ANALOG OUTPUTS Nominal Positive Full-Scale Positive Full-Scale Tempco2 Nominal VBZ Output Voltage Bipolar-Zero Output Resistance2 Nominal Peak-Peak Output Swing DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance2 POWER SUPPLIES Power Supply Range Supply Current Supply Current in Shutdown Power Dissipation3 Power Supply Sensitivity DYNAMIC CHARACTERISTICS2 Settling Time SCLK Clock Cycle time Input Clock Pulse Width Data Setup Time Data Hold Time FSYNC to SCLK active edge Setup Time SCLK to FSYNC Hold Time Minimum FSYNC High Time NOTES: 1. 2. 3. 4. Typicals represent average readings at +25C and VDD = +5V. Guaranteed by design and not subject to production test. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using VDD = +5V. Input logic should have a 1V/sec minimum slew rate. Symbol N DNL INL INL VFS/T V+FSE VBZSE V-FSE VOUTA/B TCVOUTA/B VBZ RBZ |V+FS| + |V-FS| VIH VIL IIL CIL VDD Range IDD IDD_SHDN PDISS PSS tS t1 t 2, t 3 t4 t5 t6 t7 t8 Conditions Min 12 -1 -0.05 -0.02 -0.1 -0.1 -0.1 Typ1 Max Units Bits LSB %FS %FS ppm/C %FS V %FS Volts ppm/C Volts Ohm Volts V V A pF V mA A mW %/% s ns ns ns ns ns ns ns Within 256 codes of VBZ Code = 7FFH Code = 7FFH Code = 000H Code = 800H Code = 7FFH Code = 7FFH Code 7FFH to Code 800H VDD = +5V VDD = +5V VIN = 0V or +5V, VDD = +5V 0.5 0.02 0.01 100 -0.05 +0.1 -0.05 4 100 2 1 4 +1 +0.05 +0.02 +0.1 +0.1 +0.1 2.4 0.8 1 5 4.5 5.5 2.5 40 12.5 0.0002 2 35 20 5 5 10 0 35 VIH = VDD or VIL = 0V VIH = VDD or VIL = 0V, B14=0 VIH = VDD or VIL = 0V, VDD = +5.5V VDD = +5V 10% For a 16 LSB step change 0.01 3 INTERFACE TIMING CHARACTERISTICS2,4 Clock level low or high REV PrC 20 DEC 99 -2- Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com Two's Complement, Dual 12-Bit DAC ABSOLUTE MAXIMUM RATINGS (TA = +25C, unless otherwise noted) VDD to GND ........................................................... -0.3,+6V VOUTA, VOUTB, VBZ to GND....................................... 0V, VDD Digital Input Voltages to GND ....................... 0V, VDD+0.3V Operating Temperature Range.......................... 0C to +70C Maximum Junction Temperature (TJ MAX)................. +150C Storage Temperature ................................... -65C to +150C Lead Temperature (Soldering, 10 sec) ....................... +300C Package Power Dissipation....................... (TJMAX - TA) / JA Thermal Resistance JA, SOIC-10 .....................................................206C/W AD5329 Two's Complement Coding Binary Hexadecimal Scale 0111 1111 1111 7 F F +FS 0111 1111 1110 7 F F +FS-1LSB 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000 1 SDI AD5329 0 1 SCLK 0 1 FSYNC 0 A0 X SD 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 AD5329 VDD SDA NC VOUTB VOUTA VBZ NC FSYNC Positive power supply, specified for operation at +5V. Serial Data Input, MSB first format No Connect DAC B Voltage Output (A0 = logic "1") DAC A Voltage Output (A0 = logic "0") Virtual Bipolar Zero (Active Output) No Connect Frame Sync Input, Active Low. When FSYNC returns HIGH data in the serial input register is transferred into the DAC register. Serial Clock Input, positive edge triggered Ground TABLE 2: AD5329 PIN Descriptions Pin Name Description 1 2 3 4 5 6 7 8 9 10 SCLK GND TABLE 1: AD5329 Serial-Data Word Format ADDR DATA B16 B15 B14 B13 B12 B11 A0 X SD 0 D11 D10 MSB <> <> B4 D3 B3 D2 B2 D1 B1 D0 LSB 001 000 FFF 801 800 BZS+1LSB BZS BZS-1LSB -FS+1LSB -FS SD: Shutdown is active high B14="1". Both DACs and the DACREF becomes open circuit. D2 D1 D0 Figure 1A. Timing Diagram REV PrC 20 DEC 99 -3- Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com Two's Complement, Dual 12-Bit DAC 1 SDI 0 t4 1 SCLK t3 0 1 FSYNC 0 t6 t1 t8 t7 t2 t5 Dx Dx Dx Dx AD5329 tS 1 V OUT 0 1LSB ERROR BAND Figure 1B. Detail Timing Diagram OPERATION The AD5329 provides a 12-bit, 2's complement, dual, voltage-output digital-to-analog converter. The first data bit of the 16-bit serial register is decoded to determine which DAC register (DAC A: A0= "0", DAC B: A0= "1") will be loaded with the final 12-bits of data. TABLE 3: Input Logic Control Truth Table SCLK L P L X FSYNC H L P L Register Activity No Shift Register Effect Shift One bit in from the SDA pin. Transfer SR data into DAC Register No Operation OUTLINE DIMENSIONS Dimensions shown in inches and (mm) NOTE: P = positive edge, X = don't care, SR = Shift Register The data setup and data hold times in the specification table determine the data valid time requirements. The last 12 bits of the data word entered into the serial register are held when FSYNC returns high. The internal power ON reset circuit clears the serial input registers to all zeros, and sets the two DAC registers to VBZ (zero code). All digital inputs are ESD protected with a series input resistor and parallel Zener as shown in figure 7. Applies to digital input pins SCLK, SDA, FSYNC 1K LOGIC Figure 7. Equivalent ESD Protection Circuit REV PrC 20 DEC 99 -4- Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com |
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